An input buffer circuit is a type of circuit that receives an external input signal and isolates the input signal from a load such as peripheral circuits in an integrated circuit memory. The input buffer circuit may also restore the logic levels of the input signal, increase input signal margins, provide increased driving capability, and provide better noise immunity.
The input signal may be of one logic family and the peripheral circuits may be of another logic family. For example, the input signal may be an ECL (emitter-coupled logic) signal, and an internal signal may be a CMOS (complementary metal-oxide semiconductor) level signal. In order to achieve compatibility between the two different logic families, a level conversion circuit converts, or translates, a logic signal from the ECL logic level to the CMOS logic level. A level conversion circuit should not cause excessive delay or consume a large amount of power.
In some applications, such as in a synchronous SRAM (static random access memory), it may be necessary to latch, or register, the input signal in response to a control signal. The input signal may be an address signal or a data signal. The address signal is latched in response to a clock signal. If the synchronous memory is being used as a cache in a data processing system, the clock signal may be provided by the system clock.
Set-up and hold-time specifications for the address signals are typically determined from either a rising edge or a falling edge of the clock signal. The rising edge of the clock signal is the portion of a clock cycle when the clock signal is transitioning from a logic low to a logic high voltage. The falling edge of the clock signal is the portion of a clock cycle when the clock signal is transitioning from a logic high to a logic low. The set-up time is the time that the address signal must be valid prior to the rising edge of the clock signal, in order to ensure that the proper address signal is latched. The hold-time is the time that the address signal must be maintained after the rising edge of the clock signal. The address set-up time plus the address hold-time is the address valid time. In a high speed synchronous SRAM, it is usually desirable that the set-up and hold-times be as short as possible. However, the speed at which an address signal can be buffered, level converted, and latched are determining factors in the length of the set-up and hold-times.